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This comment seems misleading to me, bit 0 of the `cr0` register enables protected mode, and that is its official name, is there a reason why it says "32 bit"? Sources: - [Intel manual](https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf) page 78 - https://wiki.osdev.org/CPU_Registers_x86#CR0
23 lines
614 B
NASM
23 lines
614 B
NASM
[bits 16]
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switch_to_pm:
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cli ; 1. disable interrupts
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lgdt [gdt_descriptor] ; 2. load the GDT descriptor
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mov eax, cr0
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or eax, 0x1 ; 3. set protected mode bit in cr0
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mov cr0, eax
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jmp CODE_SEG:init_pm ; 4. far jump by using a different segment
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[bits 32]
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init_pm: ; we are now using 32-bit instructions
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mov ax, DATA_SEG ; 5. update the segment registers
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mov ds, ax
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mov ss, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ebp, 0x90000 ; 6. update the stack right at the top of the free space
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mov esp, ebp
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call BEGIN_PM ; 7. Call a well-known label with useful code
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