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https://github.com/cfenollosa/os-tutorial.git
synced 2026-03-02 03:49:21 +00:00
Lesson 23, section 6
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@@ -13,13 +13,14 @@ isr_common_stub:
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mov es, ax
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mov fs, ax
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mov gs, ax
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push esp ; registers_t *r
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; 2. Call C handler
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cld ; C code following the sysV ABI requires DF to be clear on function entry
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call isr_handler
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; 3. Restore state
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pop eax
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pop eax
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mov ds, ax
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mov es, ax
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mov fs, ax
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@@ -39,9 +40,11 @@ irq_common_stub:
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mov es, ax
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mov fs, ax
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mov gs, ax
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push esp
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cld
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call irq_handler ; Different than the ISR code
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pop ebx ; Different than the ISR code
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pop ebx
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mov ds, bx
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mov es, bx
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mov fs, bx
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@@ -110,218 +113,186 @@ global irq15
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; 0: Divide By Zero Exception
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isr0:
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cli
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push byte 0
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push byte 0
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jmp isr_common_stub
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; 1: Debug Exception
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isr1:
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cli
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push byte 0
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push byte 1
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jmp isr_common_stub
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; 2: Non Maskable Interrupt Exception
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isr2:
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cli
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push byte 0
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push byte 2
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jmp isr_common_stub
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; 3: Int 3 Exception
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isr3:
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cli
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push byte 0
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push byte 3
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jmp isr_common_stub
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; 4: INTO Exception
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isr4:
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cli
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push byte 0
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push byte 4
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jmp isr_common_stub
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; 5: Out of Bounds Exception
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isr5:
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cli
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push byte 0
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push byte 5
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jmp isr_common_stub
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; 6: Invalid Opcode Exception
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isr6:
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cli
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push byte 0
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push byte 6
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jmp isr_common_stub
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; 7: Coprocessor Not Available Exception
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isr7:
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cli
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push byte 0
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push byte 7
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jmp isr_common_stub
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; 8: Double Fault Exception (With Error Code!)
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isr8:
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cli
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push byte 8
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jmp isr_common_stub
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; 9: Coprocessor Segment Overrun Exception
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isr9:
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cli
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push byte 0
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push byte 9
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jmp isr_common_stub
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; 10: Bad TSS Exception (With Error Code!)
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isr10:
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cli
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push byte 10
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jmp isr_common_stub
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; 11: Segment Not Present Exception (With Error Code!)
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isr11:
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cli
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push byte 11
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jmp isr_common_stub
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; 12: Stack Fault Exception (With Error Code!)
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isr12:
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cli
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push byte 12
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jmp isr_common_stub
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; 13: General Protection Fault Exception (With Error Code!)
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isr13:
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cli
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push byte 13
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jmp isr_common_stub
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; 14: Page Fault Exception (With Error Code!)
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isr14:
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cli
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push byte 14
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jmp isr_common_stub
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; 15: Reserved Exception
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isr15:
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cli
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push byte 0
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push byte 15
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jmp isr_common_stub
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; 16: Floating Point Exception
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isr16:
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cli
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push byte 0
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push byte 16
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jmp isr_common_stub
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; 17: Alignment Check Exception
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isr17:
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cli
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push byte 0
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push byte 17
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jmp isr_common_stub
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; 18: Machine Check Exception
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isr18:
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cli
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push byte 0
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push byte 18
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jmp isr_common_stub
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; 19: Reserved
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isr19:
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cli
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push byte 0
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push byte 19
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jmp isr_common_stub
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; 20: Reserved
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isr20:
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cli
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push byte 0
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push byte 20
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jmp isr_common_stub
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; 21: Reserved
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isr21:
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cli
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push byte 0
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push byte 21
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jmp isr_common_stub
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; 22: Reserved
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isr22:
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cli
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push byte 0
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push byte 22
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jmp isr_common_stub
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; 23: Reserved
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isr23:
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cli
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push byte 0
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push byte 23
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jmp isr_common_stub
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; 24: Reserved
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isr24:
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cli
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push byte 0
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push byte 24
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jmp isr_common_stub
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; 25: Reserved
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isr25:
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cli
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push byte 0
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push byte 25
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jmp isr_common_stub
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; 26: Reserved
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isr26:
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cli
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push byte 0
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push byte 26
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jmp isr_common_stub
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; 27: Reserved
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isr27:
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cli
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push byte 0
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push byte 27
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jmp isr_common_stub
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; 28: Reserved
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isr28:
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cli
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push byte 0
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push byte 28
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jmp isr_common_stub
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; 29: Reserved
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isr29:
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cli
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push byte 0
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push byte 29
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jmp isr_common_stub
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; 30: Reserved
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isr30:
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cli
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push byte 0
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push byte 30
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jmp isr_common_stub
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; 31: Reserved
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isr31:
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cli
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push byte 0
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push byte 31
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jmp isr_common_stub
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@@ -116,13 +116,13 @@ char *exception_messages[] = {
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"Reserved"
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};
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void isr_handler(registers_t r) {
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void isr_handler(registers_t *r) {
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kprint("received interrupt: ");
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char s[3];
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int_to_ascii(r.int_no, s);
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int_to_ascii(r->int_no, s);
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kprint(s);
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kprint("\n");
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kprint(exception_messages[r.int_no]);
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kprint(exception_messages[r->int_no]);
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kprint("\n");
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}
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@@ -130,15 +130,15 @@ void register_interrupt_handler(uint8_t n, isr_t handler) {
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interrupt_handlers[n] = handler;
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}
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void irq_handler(registers_t r) {
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void irq_handler(registers_t *r) {
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/* After every interrupt we need to send an EOI to the PICs
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* or they will not send another interrupt again */
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if (r.int_no >= 40) port_byte_out(0xA0, 0x20); /* slave */
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if (r->int_no >= 40) port_byte_out(0xA0, 0x20); /* slave */
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port_byte_out(0x20, 0x20); /* master */
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/* Handle the interrupt in a more modular way */
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if (interrupt_handlers[r.int_no] != 0) {
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isr_t handler = interrupt_handlers[r.int_no];
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if (interrupt_handlers[r->int_no] != 0) {
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isr_t handler = interrupt_handlers[r->int_no];
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handler(r);
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}
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}
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@@ -71,7 +71,13 @@ extern void irq15();
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#define IRQ14 46
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#define IRQ15 47
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/* Struct which aggregates many registers */
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/* Struct which aggregates many registers.
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* It matches exactly the pushes on interrupt.asm. From the bottom:
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* - Pushed by the processor automatically
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* - `push byte`s on the isr-specific code: error code, then int number
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* - All the registers by pusha
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* - `push eax` whose lower 16-bits contain DS
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*/
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typedef struct {
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uint32_t ds; /* Data segment selector */
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uint32_t edi, esi, ebp, useless, ebx, edx, ecx, eax; /* Pushed by pusha. */
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@@ -80,10 +86,10 @@ typedef struct {
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} registers_t;
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void isr_install();
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void isr_handler(registers_t r);
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void isr_handler(registers_t *r);
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void irq_install();
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typedef void (*isr_t)(registers_t);
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typedef void (*isr_t)(registers_t*);
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void register_interrupt_handler(uint8_t n, isr_t handler);
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#endif
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@@ -5,7 +5,7 @@
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uint32_t tick = 0;
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static void timer_callback(registers_t regs) {
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static void timer_callback(registers_t *regs) {
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tick++;
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UNUSED(regs);
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}
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